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CX335 Technical Manual Page 15

Circuit Description

For clarity the internal circuitry of the CX335 is best described in sections. Both left and

right audio inputs are passed through a Voltage Controlled Amplifier (VCA) to the

balanced output sections; a signal level detector below 200Hz; a signal level detector

above 200Hz ; peak limiter detector; display circuits

7.01 The Audio Path

Due to the fact that both Left and Right channels are basically identical, only one channel

is described here. Any component references are given for the Left channel with the Right

channel in parentheses.

Signals are fed into an electronically balanced input opamp IC1a (IC6a) with a gain of

-6dB. The output of this opamp drives three routes:-

One route is to the Bypass switch where it can be connected directly to the output stage.

One route is into the side chain filters (described later.)

One route is to the Voltage Controlled Amplifier (VCA).

An industry standard high performance VCA is used to increase or decrease gain, IC3

(IC8). The VCA used is the dBX 2150A and the device has a current output which can be

measured with an oscilloscope on pin 1 of IC1b (IC6b). The gain of the VCA is controlled

by a DC voltage onto pin 3. Note: If pin 3 is grounded, then signal is passed with no gain.

This factor can be a useful service aid.

The VCA feeds a Peak Limit rectifier IC13a (IC17a) and passes into the Peak Limit

comparator IC4a (IC9a), where the signal level is compared with a DC voltage derived

from the front panel potentiometer VR3. This sets the bias level for two high speed

diodes D6 & D7 (D16 & D17) that will clip off any signal peaks greater than the bias.

Clipping causes IC4a (IC9a) to generate charge pulses to the limiter control voltage

IC19b and IC13b, this circuit is common to both audio channels ensuring no stereo image

shift. The Peak / Limiting LED indicator driven by IC19a is lit when audio peaks cause

limiting, and not illuminated during the limit envelope.

The Bypass switch selects the input signal buffer or the signal from the peak limiter and

feeds this to the balanced output stage IC5 (IC10) which has gain of +6dB.

7.02 The Side Chain

The signal from the input stage is passed through the 200Hz high-pass filter (HPF) IC2a

(IC7a). This is summed with an anti-phase signal from IC2b (IC7b) to produce a low-pass

filter (LPF) output of signals below 200Hz. For each audio input there are two signals

which are converted to DC using log law dual detectors, SSM2120, where IC12 is

configured to process the HPFs and IC16 is processing the LPFs. The LPF outputs of

these detectors are summed and passed to the threshold/ratio circuit which in turn feeds

the long time constant attack and release circuit and the HPF outputs are summed and

sent to the threshold/ratio circuit feeding the short time constant attack and release

circuit.

The Threshold potentiometer VR1 sets a DC bias to IC11a for the HPF and IC15a for the

LPF, this determines the signal level that will cause compression. This level is then

amplified by the Ratio stage IC15b for LPF and IC11b for HPF. The ratio amplifier has a

gain of 10 when 'Hard' is selected adjustable by presets PR7 and PR8, and an antilog

response with a maximum gain of 10 when 'Soft' is selected. The antilog element uses a

pair of transistors T3/T4 for LPF and T1/T2 for HPF, which are biased into the log part of

their curve by presets PR9 and PR6.

The DC control voltages from these stages are divided by the Ratio potentiometers VR2,

which feeds the LPF and HPF envelope attack and release circuits. The LPF envelope

circuit using IC21a, IC22a and IC22b has a slow attack with a 50mS hold and a

programme dependant decay. The HPF envelope circuit using IC20a and IC20b has a

much faster programme dependant attack, no hold and a programme dependant decay.

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